Please give us a detailed overview of your session and why attendees will be excited to hear about it.
Session title would be “Open Source Processor IP for High Volume Production - the CORE-V Family of RISC-V cores” with the intent to provide the Eclipse community with an overview of the RISC-V instruction set architecture and to describe the CORE-V family of open-source cores that implement the RISC-V ISA
RISC-V (pronounced “risk-five”) is an open, free ISA enabling a new era of processor innovation through open standard collaboration. Born in academia and research, RISC-V ISA delivers a new level of free, extensible software and hardware freedom on architecture, paving the way for the next 50 years of computing design and innovation.
The final Unprivileged Specification, a Privileged Specification, and a suite of RISC-V software tools including a GNU/GCC software tool chain, GNU/GDB debugger (upstream), an LLVM compiler, a Spike ISA simulator, QEMU (upstream), and a verification suite is available for download now.
CORE-V is a series of RISC-V based open-source processor cores with associated processor subsystem IP, tools and software for electronic system designers. The CORE-V family provides quality core IP in line with industry best practices in both silicon and FPGA optimized implementations. These cores can be used to facilitate rapid design innovation and ensure effective manufacturability of production SoCs.
Ensure that you let us know:
- What level of knowledge should attendees have before walking into your session
- Attendees should have general knowledge of programming RISC processors using open source tools
- What will your session accomplish and what will attendees walk away having learned
- A better understanding of what RISC-V is and where it came from as well as knowledge of the CORE-V family of open-source processor cores.