Taming complex chip designs with beautiful diagrams

In this talk we will show how text-based design, combined with graphical views, makes chip designers more productive.

Graphical diagrams are a powerful tool to document and review chip designs. While it is easy to convey a simple design in a visual way, things get out of control very easily. Likewise, it is not practical to manually draw a large number of lines between two modules. In addition, much of the time needed for graphical design entry is spent on placing objects on the screen, making them look nice, or on squeezing extra functionality into a congested design. So graphical editors are not practical for complex chip design.

At Sigasi, we favor text based design entry (in VHDL or SystemVerilog) combined with graphical views that visualize the design. These graphical Views are automatically generated, so you always have an up to date graphical way to explore a design.
For complex designs however, these diagrams still contain too much details. To limit the amount of details we developed an Xtext DSL to simplify and enhance diagrams, and allow multiple views on the same code.

In this talk we’ll discuss the challenges we faced to create graphical views. A lot of experimentation was required to find the right visualisation framework, layouting algorithm and graphical elements. We also present the several technical challenges we encountered while integrating these solutions in Eclipse.

Schedule info
Session Time Slot(s): 
Tuesday, October 24, 2017 - 15:15 to 15:50

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