This talk will provide a brief overview of Open-Source HW activity across the industry, barriers to adoption of Open-Source HW and challenges associated with SoC design. Lessons learned related to the OpenHW Group Governance model and adoption of CORE-V Family of open source RISC-V cores will also be presented. The CORE-V Family is an OpenHW Group project to develop, deploy, and execute pre-silicon functional verification and SoC based development kits of the CORE-V family of open-source RISC-V cores. Written in SystemVerilog, CORE-V open-source IP cores match the quality of IP offered by established commercial providers and are verified with state-of-the-art, auditable flows.
Objective of the presentation:
This talk will provide a brief overview of Open-Source HW activity across the industry, barriers to adoption of Open-Source HW and challenges associated with SoC design (see below)
Attendee pre-requisites - If none, enter "N/A":
N/A
