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  5. Towards a Comprehensive Open Source IoT RISC-V Stack

Towards a Comprehensive Open Source IoT RISC-V Stack

Session details
Status: 
Accepted
Speaker(s): 
Frédéric Desbiens (Eclipse Foundation)
Alexander Fedorov (ArSysOp)
Experience level: 
Beginner
Tags: 
iot
RISC-V
Open Source
Session Track: 
IoT & Edge
Session Type: 
Standard

The RISC-V instruction set is now taking the world by storm. Since it is open source, many organizations designing their own processors and boards have leveraged it. If you are an IoT and Edge developer, you probably don't pay too much attention to processor instruction sets. This is understandable. However, IoT devices and edge nodes often benefit from being customized for specific use cases. Given this, it could make sense for you to leverage open source hardware and software together. But where will you find a comprehensive RISC-V based open source stack?
 
In this presentation, you will learn about the OpenHW Group, a not-for-profit global organization aiming to boost the adoption of open-source processors. You will explore its CORE-V Family of RISC-V based open source cores as well as the associated processor subsystem IP, tools and software. Moreover, you will discover how the OpenHW Group and the Eclipse Foundation collaborate to give birth to a comprehensive open source stack including everything from processor cores to fundamental toolchains, integrated development environments as well as IoT and Edge Computing frameworks and platforms.

Objective of the presentation: 
Introduce developers to the CORE-V family of open source processors and the various Eclipse projects they can leverage with them.
Attendee pre-requisites - If none, enter "N/A": 
Familiarity with IoT use cases.
Schedule info
Time: 
28 Oct 2021 - 16:10 to 28 Oct 2021 - 16:40
Room: 
Room 4
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